[linux-nvidia-6.17] Use architecture specific HBM training status register#331
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This looks good to me.
Acked-by: Matthew R. Ochs <mochs@nvidia.com>
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@ankita-nv Are there plans to upstream this patch? |
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Yeah, I'll post it shortly after internal review. |
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Ankit requested that we hold on getting this integrated. |
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…diness check Blackwell-Next GPUs report device readiness via the CXL DVSEC Range 1 Low register (offset 0x1C) instead of the BAR0 HBM training register used by GB200. The GPU memory readiness is checked by polling for the Memory_Active bit (bit 1) for the Memory_Active_Timeout (bits 15:13). Add runtime detection by checking the presence of the DVSEC register. Route to the new method if present, otherwise continue using the legacy approach. Signed-off-by: Ankit Agrawal <ankita@nvidia.com>
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Blackwell-Next GPUs use a different BAR0 offset (0xAD00BC) for the HBM
training status register than GB200 (0x200BC). Add runtime detection by
reading the architecture field from PMC BOOT_42 and selecting the
appropriate offset when polling for device readiness.
Signed-off-by: Ankit Agrawal ankita@nvidia.com